The present invention refers to an apparatus having a DC-DC converter, in particular a DC-DC converter having a semiconductor switch, which is driven in such a way that, despite a high switching speed, it exhibits small voltage overshoots during switching. This invention also refers to Zero Overvoltage Switching (ZOS), i.e. a voltage transformer having low voltage excessive peaks.
In power electronics, there are countless topologies and circuits which switch a current path on and off with the help of a transistor.
The current path to be switched consists of an electrical conductor and a conductor loop that, due to natural laws, also forms a parasitic inductance. This inductance, typically in the range from 1 to 100 nH, prevents the switching process from taking place at any desired speed. With increasingly faster switching processes in the range from 1 to 1000 ns (depending on the power class), high switch-off overvoltages occur at the switching element, i.e. at the transistor, especially when switching off.
FIG. 8a and FIG. 8b show a schematic block circuit diagram of a state of the art DC-DC converter 1000 as well as a schematic graph with a progression of a voltage U and a current I through a MOSFET 1002 (MOSFET=metal oxide semiconductor field-effect transistor), which are plotted on a common time axis t. For example, the DC-DC converter 1000 has a gate resistance R of, e.g., 10 ohms, which results in a significantly reduced switching speed compared to an absence of the gate resistance. Nevertheless, when switching off the MOSFET 1002, overvoltages or an overshoot 1004 may occur, this may be described by exceeding a nominal voltage Unom up to a maximum voltage level Umax, which means that an overshoot 1004 may be defined as Umax-Unom or the amount thereof. If the voltage of a voltage source or the voltage Unom to be reached is, e.g., 800 V, Umax may reach up to 1000 V, so that the overvoltage 1004 may have a value of 200 V. These are only exemplary values. The subsequent oscillations 1006 of the current and the voltage shown in FIG. 8b may cause problems as to the electromagnetic compatibility (EMC).
In other words, FIG. 8a and FIG. 8b show a classical double pulse test setup with real devices, i.e. they do not show ideal switches or diodes.
This problem of switch-off overvoltage due to the parasitic inductance has been discussed by experts for decades. Known remedies are, e.g., braking the switching process by means of larger gate series resistances (gate pre-resistance). However, this leads to high and undesirable switching losses.
Other concepts use a changed topology, for example resonant circuits, accordingly having other advantages and disadvantages.
Other concepts aim at minimizing the commutation inductance by adding pulse capacitors or so-called snubbers.
Snubbers are also means for achieving Zero Voltage Switching proposed in “3.38 MHz operation of 1.2 kV SiC MOSFET with integrated ultra-fast gate drive” (2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WIPDA)).
However, new challenges also arise, e.g. through SiC switches and/or GaN switches and/or modern and very fast Si switches, such as IGBT 5 and/or Si-MOSFETs. If allowed, these may switch extremely fast, so that switching durations in the range of 10 ns and below may be achieved with the switch. For years, experts have therefore been trying to construct low-inductance geometries of the commutation cell. This includes reducing conductor spacing, inserting foils instead of wires, forming flat terminal pads and using printed circuit boards and the SMD technology (SMD=surface mounted device) instead of discrete packages housings and modules.
Therefore, concepts enabling low circuit losses and low overvoltages would be desirable for the control of DC-DC converters.